1. Field
Various embodiments of the present invention relate to an integrated circuit, and more particularly, to a technology for decoding a binary code and performing a logic operation.
2. Description of the Related Art
In general, binary codes (i.e., encoded signals) are used as an input signal of a semiconductor device to decrease the bit number of the input signal. For example, when 1024 word lines are included in a memory device, 1024 selection signals have to be used to select one word line. However, it may be difficult to transmit/receive 1024 selection signals. Thus, an address formed of a 10-bit binary code is used to transmit/receive selection information.
FIG. 1 shows a logic operation of a binary code and ordinary signals that are not a binary code.
Referring to FIG. 1, the logic operation, e.g., an AND operation or an OR operation, of a 3-bit binary code BCODE<0:2> and 8 ordinary signals S<0> to S<7> may not be directly performed. The 3-bit binary code BCODE<0:2> has to be decoded into 8 signals DEC<0> to DEC<7> by using a decoder 110, and then the decoded 8 signal's DEC<0> to DEC<7> are logically combined with the 8 ordinary signals S<0> to S<7> in a logic operation circuit 120.
FIG. 2 illustrates a circuit for generating a precharge/active flag signal IMPRE_FLAG that is used to support an implicit precharge (imPRE) function in a memory device.
The implicit precharge function of a memory device denotes an operation in which, if a memory bank corresponding to an active command is in a precharge state, an activation operation is directly performed, and if the memory bank corresponding to the active command is not in a precharge state (i.e., if the memory bank is in an active state), a precharge operation is performed first and then an active operation is performed a predetermined time later. For example, where a memory bank 0 included in a memory device is in an active state and a memory bank 1 is in a precharge state, when an active command for the memory bank 0 is applied, the memory bank 0 is precharged and then an active operation is performed on the memory bank 0. Meanwhile, when an active command for the memory bank 1 is applied, an active operation is directly performed on the memory bank 1. That is, when an active command is applied to a memory device, the precharge/active flag signal IMPRE FLAG indicates whether the applied active command corresponds to an active bank or a precharged bank.
Referring to FIG. 2, the circuit for generating the precharge/active flag signal IMPRE_FLAG includes a decoder 210, and a logic operation circuit 220.
The decoder 210 decodes a bank address BA<0:2>, which is a binary code, to generate bank selection signals BS<0:7>. The bank address BA<0:2> is inputted along with an active command, and the bank selection signals BS<0:7> are activated when a corresponding bank is selected. For example, when a bank 3 is selected based on the bank address BA<0:2>, a bank selection signal BS<3> is activated.
The logic operation circuit 220 performs a logic operation on the bank selection signals BS<0:7> and active signals RACT<0:7> to generate the precharge/active flag signal IMPRE_FLAG. The active signals RACT<0:7> represent whether the corresponding bank is in an active state or a precharge state. To take an example when a bank 2 is in an active state, the active signal RACT<2> has a logic high level, and when the bank 2 is in a precharge state, the active signal RACT<2> has a logic low level. When a bank selection signal and a corresponding active signal are activated, in other words, when an active command corresponding to a bank that is in an active state at present is applied, the logic operation circuit 220 activates the precharge/active flag signal IMPRE_FLAG. Otherwise, the logic operation circuit 220 deactivated the precharge/active flag signal IMPRE_FLAG. The fact that the precharge/active flag signal IMPRE_FLAG is activated means that although an active command is applied to the memory device, the active target bank is not in an active state and thus a precharge operation has to be performed prior to an active operation. Meanwhile, the fact that the precharge/active flag signal IMPRE_FLAG is deactivated means that the active target bank is in a precharge state and thus an active operation may be performed immediately.
FIGS. 3A and 3B are detailed diagrams of the logic operation circuit 220 shown in FIG. 2.
FIG. 3A illustrates an example of the logic operation circuit 220. Referring to FIG. 3A, the logic operation circuit 220 includes AND gates 311 to 318 and an OR gate 319. When the corresponding signals are simultaneously activated among the active signals RACT<0:7> and the bank selection signals BS<0:7>, the logic operation circuit 220 activates the precharge/active flag signal IMPRE_FLAG. For example, when the active signal RACT<4> and the bank selection signal BS<4> are simultaneously activated, or when the active signal RACT<6> and the bank selection signal BS<6> are simultaneously activated, the precharge/active flag signal IMPRE_FLAG is activated.
Although the logic operation circuit 220 of FIG. 3A is simple, the multi-input OR gate 319 may not be used in actual applications due to its large fan-in. Furthermore, AND gates are generally implemented by using a NAND gate and an inverter, and OR gates are generally implemented by using a NOR gate and an inverter. Thus, the logic operation circuit 220 may have a structure shown in FIG. 3B.
As described above, binary codes are widely used in semiconductor devices, but the binary codes have to be decoded for the logic operation with other signals. While binary codes go through the decoding process, a delay occurs, and this leads to a delay of a final output signal. Also, since a decoder circuit is required for the decoding process, the circuit area may be increased.